Voltage regulator with high accuracy and high power supply rejection ratio

ABSTRACT

A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor&#39;s gate. The PMOS transistor&#39;s source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp&#39;s second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp&#39;s first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional Patent Application Ser. Nos. 61/165,754, filed Apr. 1, 2009 and 61/168,813, filed on Apr. 13, 2009, which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

This disclosure relates generally to an electrical circuit for a voltage regulator, and more particularly to an integrated circuit for a voltage regulator using feedback control mechanisms.

BACKGROUND

A voltage regulator is an electrical regulator designed to automatically maintain a constant voltage level. A voltage regulator takes an environmentally sensitive voltage input and generates a stable output voltage. Therefore, constructing a voltage regular with an accurately regulated output voltage over various environments (e.g. process, voltage, and temperature, “PVT”) is an important design goal. Precise control of load regulation (ΔV_(OUT)/ΔI) across various environments is desirable. For example, in embedded Dynamic Random Access Memory (eDRAM) devices, accurate bit-line reference voltage is required for precise operations. In general, a voltage regulator should be able to isolate impacts of both source (supply) and sink charge from the regulated output and overcome over-voltage (or “hiccup”) problem. Further, a voltage regulator should be able to overcome instability at low output currents.

Another important characteristic of a voltage regulator is a high power supply rejection ratio (PSRR), which is used to describe the amount of noise from a power supply that can be rejected. The value of PSRR depends on the power supply being considered, thus the PSRR for the higher supply voltage is different than the PSRR of the lower supply voltage. The PSRR is defined as the ratio of the change in power supply voltage (ΔV_(DD)) to the change in output voltage (ΔV_(OUT)) caused by the change in the power supply, PSRR=ΔV_(DD)/ΔV_(OUT.)

An ideal voltage regulator would have infinite PSRR. A real voltage regulator would have a finite PSRR, but a higher PSRR across all frequency (especially around chip resonance frequency of about a few MHz to 100 MHz) is desirable. Higher PSRR is crucial in many modern System on Chip (SOC) or System in Package (SiP) designs where power supply noise immunity is very important.

There are prior arts for producing voltage regulators, but some encounter over voltage (or “hiccup”) problem and/or low-load current instability problem. Some have improved on those problems but have not accurately regulated output voltage and/or have poor PSRR.

FIG. 1A illustrates an example of a conventional voltage regulator circuit. The circuit 100 suffers from over-voltage (or hiccup) problem. When load current rapidly changes from a large value to a very small value, the feedback loop 102 locked up because the feedback control loop 102 cannot remove the excess charge from the output capacitor 101 fast enough. Also, when the output current level is below a minimum required output current value, there is instability at the output voltage because the feedback loop 102 cannot function as designed due to insufficient gain of the loop. (The loop gain is proportional to the transconductance g_(m) and output resistance R_(out), and g_(m) is proportional to the drain current through the PMOS 104.) Also, the circuit has a poor PSRR at mid to high power supply noise frequency, typically around a few MHz to 100 MHz, because the feedback loop 102 cannot respond fast enough for output (V_(REG)) change resulting from power supply noise. The circuit response is slow due to the limited bandwidth and cannot respond to high frequency noise. Further, there is no trimming capability for high accuracy V_(REG) output in the circuit 100 shown in FIG. 1A.

FIG. 1B illustrates the output current-voltage plot of an example conventional voltage regulator circuit as shown in FIG. 1A. As the current changes from zero to a small value (minus value means the current flows out), the output voltage changes rapidly until the output voltage reaches saturation (slower change), mainly due to the operation point of the PMOS transistor 104. Therefore, the prior art circuit suffers from a steep output voltage variation as shown in FIG. 1B. For example, an output voltage variation of about 30 mV was estimated from a conventional circuit similar to the circuit 100 shown in FIG. 1A. Further, a poor phase margin (less than 50 degrees) from the conventional circuit 100 can require a large decoupling capacitance of around 200 pF.

Accordingly, new methods and circuits for a voltage regulator to improve accuracy and overcome over-voltage problem, instability at low output currents, and poor PSRR are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1A illustrates an example of a conventional voltage regulator circuit;

FIG. 1B illustrates the output current-voltage plot of an example conventional voltage regulator circuit as shown in FIG. 1A;

FIG. 2A illustrates an exemplary embodiment of a voltage regulator circuit according to an embodiment of the invention;

FIG. 2B illustrates the output current-voltage plot of an example voltage regulator circuit as shown in FIG. 2A, showing substantially smaller load regulation variation;

FIG. 2C illustrates one example of implementing the bias voltage to put the NMOS transistor 504 in saturation mode;

FIG. 2D illustrates another example of implementing the bias voltage to put the NMOS transistor 504 in saturation mode;

FIG. 2E illustrates an embodiment of a voltage regulator circuit according to the invention;

FIG. 3A and FIG. 3B illustrate exemplary embodiments of a voltage regulator circuit according to one or more embodiments of the invention; and

Fig. 3C illustrates an embodiment of a voltage regulator circuit according to the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

A voltage regulator circuit to achieve high accuracy and high PSRR is provided. Throughout the various views and illustrative embodiments of the present invention, like reference numbers are used to designate like elements.

FIG. 2A illustrates an exemplary embodiment of a voltage regulator circuit according to an embodiment of the invention. The output stage PMOS transistor 202 in the circuit 200 provides sufficient current for output load. The bias voltage (V_(bias)) keeps the NMOS transistor 204 at saturation mode independent of environments.

FIG. 2B illustrates the output current-voltage plot of an example voltage regulator circuit as shown in FIG. 2A, showing substantially smaller load regulation variation. Because the NMOS transistor 204 is at saturation mode, the output voltage variation from the load current change is relatively small (e.g. ˜10 mA). The NMOS transistor 204 in saturation mode provides current (e.g. ˜60 μA) to keep the required input voltage swing to the Op-Amp 206 small, which is related to the small output voltage swing resulting from load current change as shown in FIG. 2B. Also, because of the small output voltage swing required for load current change, it is easier to provide current when many voltage regulators are connected together. Further, the circuit 200 in FIG. 2A requires less decoupling capacitance needed to achieve better than 60 degrees phase margin compared to conventional design, due to smaller load regulation ΔV_(OUT)/ΔI. Because of the bias voltage in the circuit 200, it further reduces PVT variation for the regulated output voltage. The biasing voltage/current can be designed to be adjustable, therefore output voltage variation/accuracy can be adjusted depending on applications to achieve best power and performance. The circuit 200 can be used to provide an accurate output voltage for various applications, e.g. a memory bit-line reference voltage, such as V_(DD) or V_(SS) sensing in eDRAM.

FIG. 2C illustrates one example of implementing the bias voltage to put the NMOS transistor 204 in saturation mode. The circuit 300 has another NMOS transistor 302 connected to a current source 304 (adjustable) to provide the bias voltage.

FIG. 2D illustrates another example of implementing the bias voltage to put the NMOS transistor 204 in saturation mode. The circuit 400 has another NMOS transistor 302 connected to the power supply V_(DD) through a variable resistor R3 to provide the bias voltage.

FIG. 2E illustrates another embodiment of a voltage regulator circuit according to the invention, similar to the circuit in FIG. 2A. The circuit 500 includes an NMOS transistor 502 connected to the op-amp 506 instead of a PMOS transistor compared to the circuit 200 in FIG. 2A. Also, the circuit 500 includes a PMOS 504 biased by V_(bias) to keep it in saturation mode, instead of an NMOS 204 compared to the circuit 200 in FIG. 2A. The circuit 500 is a different embodiment of this invention, and a person skilled in the art will appreciate that there can be many different embodiment variations of the invention.

FIG. 3A illustrates an exemplary embodiment of a voltage regulator circuit according to an embodiment of the invention. The circuit 600 further adds more components on the circuit 200 shown in FIG. 2A. The circuit 600 uses one comparator (e.g. high bandwidth Op Amp) with dual outputs, i.e. Out 1 and Out 2. The first feed back loop 602 is under the regular load condition, and the driver PMOS 606 between the power supply voltage (V_(DD)) and the regulator output (V_(REG)) provides the source current to the output load. An op-amp with a reference voltage input V_(REF) through RC elements to its inverting input has the op-amp's first output (Out 1) connected to the gate of the PMOS transistor 606. The source and drain of the PMOS transistor 606 are each connected to the power supply voltage (V_(DD)) and to the voltage regulator output V_(REG). The voltage regulator output is also connected to an NMOS transistor 608 and a series of two resistors R6 and R7. The NMOS transistor 608 is biased to operate in saturation mode and the non-inverting input of the op-amp is connected in between the two resistors R6 and R7 for the first feedback loop 602, where R6 is variable.

Further, the op-amp's second output (Out 2) is connected to the gate of the NMOS transistor 608 through an AC-coupling capacitor C2 for the second feedback loop 604. The op-amp's first output (Out 1) is connected to the power supply voltage (V_(DD)) through a capacitor C3 to further improve high frequency PSRR. The voltage regulator input V_(REF) is connected to RC elements to filter out input noise and the voltage regulator output is connected to a de-coupling capacitance C1 to filter out output noise. The current capacity of the NMOS transistor 608 is adjustable and the bias voltage to the NMOS transistor 608 can be supplied using a second NMOS transistor 610 connected to a current source, where the gate and drain of the second NMOS transistor 610 are connected together and the current source is also adjustable.

The second feed back loop 604 quickly responds and corrects output over-voltage conditions. For example, any abrupt output voltage change is fed back and AC coupled by the capacitor C2 to activate the pull-down circuit that includes the NMOS transistor 608 to quickly discharge excess charge at the output. The NMOS transistor 608 has variable current capacity (trim-able). Therefore, high frequency PSRR of this voltage regulator circuit 600 is greatly improved by including the second loop 604 with AC coupling capacitance C2. The DC bias (through R8) and trim-able pull-down transistor 608 provides a reasonable pass current to prevent a low-load instability issue.

Therefore, the novel regulator not only has high PSRR but also resolves over-voltage and low-load instability issues dynamically, which minimizes power waste during regular load operation. In some embodiments, the regulator has a small gate-source voltage (Vgs) for NMOS transistor 608 to prevent instability issue at low-load or no-load situation and sink excess charge due to low frequency over-voltage. In high frequency over-voltage situation, high voltage from Out 2 is AC coupled to the Vgs of NMOS transistor 608 to quickly sink large amount of excess charge. With different gate-source biases to NMOS 608 at DC/low-frequency and high-frequency, it minimizes DC power waste under regular load situations as result in improving the voltage regulator's current supply efficiency.

A tracking capacitor (C3) between the power supply V_(DD) and driver 606 (pass-element between regulator in and regulator out) is utilized to further improve high frequency PSRR. Trim-able V_(REG) output voltage (through e.g. R6) can be used to achieve higher accuracy voltage output voltage. Also, the comparator's reference input noise is filtered (e.g. RC elements coupled to the V_(REF) input).

The advantageous features of the circuit 600 include using only a single comparator amplifier (the Op Amp) design to achieve high PSRR as well as resolving critical over-voltage and low-load instability issues of voltage regulators. The AC coupling path quickly discharges over-voltage at the regulator output due to sudden change of the load, and adjustable pull-down network, providing enough current to have adequate g_(m) of the PMOS driver 606 to maintain large enough loop gain in order to address low-load instability issue. Tracking capacitance between the power supply and driver 606 (pass-element between regulator in and regulator out) further improves high-frequency PSRR. The V_(REG) output and minimum-load current can be adjusted for high accuracy and stability. Other advantages include that this regulator do not require feed-back loop 602 to be out of control before it can function for preventing the over-voltage issue. Further, the regulator has trimming capability for high accuracy V_(REG) output and minimum-load current for stability.

FIG. 3B illustrates another example embodiment of a voltage regulator circuit according to an embodiment of the invention. Compared with the circuit 600 depicted in FIG. 3A, the amplifier Op Amp with dual outputs is replaced by two amplifiers (Op Amp 1 and Op Amp 2) each have a single output OUT 1 and OUT 2.

Fig. 3C illustrates another embodiment of a voltage regulator circuit according to the invention. The op-amp with a voltage input to its inverting input through RC elements has the op-amp's output connected to the gate of an NMOS transistor 706. The source and drain of the NMOS transistor 706 are each connected to the ground and to the voltage regulator output. The voltage regulator output is also connected to a PMOS transistor 708 and a series of two resistors R9 and R10. The PMOS transistor 708 is biased to operate in saturation mode and the non-inverting input of the op-amp is connected in between the two resistors R9 and R10 for a first feedback loop 702, where R9 is variable. The op-amp's output can be connected to the ground through a capacitor C4 to improve high frequency PSRR. The voltage regulator input VREF is connected to the op-amp's inverting input through RC elements to filter out input noise and the voltage regulator output VREG is connected to a de-coupling capacitance C6 to filter out output noise. The current capacity of the PMOS transistor 708 can be adjustable and the bias voltage to the PMOS transistor 708 can be supplied using a second PMOS transistor 710 connected to a variable current source, where the gate and drain of the PMOS transistor 710 are connected together. A skilled person in the art will appreciate that there can be many embodiment variations of this invention.

Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

1. A voltage regulator circuit, comprising: a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, and a first op-amp output; a PMOS transistor; a first NMOS transistor; and a bias circuit outside the op-amp, wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and the bias circuit is electrically coupled to the gate of the first NMOS transistor and configured to bias the first NMOS transistor in saturation mode.
 2. The voltage regulator circuit of claim 1, wherein a capacitor is connected to the voltage output and the ground.
 3. The voltage regulator circuit of claim 1, wherein the bias circuit comprises a second NMOS transistor and a current source circuit connected to a gate and a drain of the second NMOS transistor, wherein a source of the second NMOS transistor is connected to the ground and the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor through a third resistor.
 4. The voltage regulator circuit of claim 3, wherein the current source circuit includes a variable resistor connected to the power supply voltage.
 5. The voltage regulator circuit of claim 3, wherein the op-amp further comprises a second op-amp output connected to the gate of the first NMOS transistor through a capacitor.
 6. The voltage regulator circuit of claim 5, wherein the first NMOS transistor is adjustable to change a current capacity of the first NMOS transistor.
 7. The voltage regulator circuit of claim 1, wherein the first resistor is adjustable.
 8. The voltage regulator circuit of claim 1, wherein the first op-amp output is connected to the power supply through a capacitor.
 9. The voltage regulator circuit of claim 1, wherein the voltage input is connected to the inverting input of the op-amp through another resistor and the inverting input is connected to the ground through a capacitor.
 10. A voltage regulator circuit, comprising: a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, and an op-amp output; an NMOS transistor; a first PMOS transistor; and a bias circuit outside the op-amp, wherein the reference voltage input is connected to the inverting input, the op-amp output is connected to a gate of the NMOS transistor, a source of the NMOS transistor is connected to a ground, a drain of the NMOS transistor is connected to the voltage output and a drain of the first PMOS transistor, a source of the first PMOS transistor is connected to a power supply voltage, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input of the op-amp, a second resistor is connected to the first resistor and the ground, and the bias circuit is electrically coupled to the gate of the first PMOS transistor and configured to bias the first PMOS transistor in saturation mode.
 11. The voltage regulator circuit of claim 10, wherein a first capacitor is connected to the voltage output and the ground.
 12. The voltage regulator circuit of claim 10, wherein the bias circuit comprises a second PMOS transistor and a current source circuit connected to a gate and a drain of the second PMOS transistor, wherein a source of the second PMOS transistor is connected to the power supply voltage and the drain of the second PMOS transistor is connected to the gate of the first PMOS transistor through a third resistor.
 13. The voltage regulator circuit of claim 12, wherein the current source circuit includes a variable resistor connected to the ground.
 14. The voltage regulator circuit of claim 10, wherein the first PMOS transistor is adjustable to change a current capacity of the first PMOS transistor.
 15. The voltage regulator circuit of claim 10, wherein the first resistor is adjustable.
 16. The voltage regulator circuit of claim 10, wherein the op-amp output is connected to the ground through a capacitor.
 17. The voltage regulator circuit of claim 10, wherein the reference voltage input is connected to the inverting input of the op-amp through another resistor and the inverting input is connected to the ground through a capacitor.
 18. A voltage regulator circuit, comprising: a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, a first op-amp output and a second op-amp output; a PMOS transistor; a first NMOS transistor; and a second NMOS transistor; wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and a bias voltage is connected to the gate of the first NMOS transistor so that the first NMOS transistor is in saturation mode, wherein the bias voltage is supplied by a current source circuit connected to a gate and a drain of the second NMOS transistor, a source of the second NMOS transistor is connected to the ground, the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor through a third resistor, wherein the current source circuit includes a fourth resistor connected to the power supply voltage, and the second op-amp output is connected to the gate of the first NMOS transistor through a capacitor.
 19. The voltage regulator circuit of claim 18, wherein the first NMOS transistor is adjustable to change a current capacity of the first NMOS transistor.
 20. The voltage regulator circuit of claim 18, wherein the first resistor is adjustable. 